The invention relates to an integrated memory circuit, comprising a matrix in which each column comprises its own sense amplifier circuit for forming an externally presentable output signal on a respective sense amplifier circuit output.
A circuit of the general kind set forth above is known from U.S. Pat. No. 3,930,239.
Said patent specification describes an integrated memory circuit in which the use of an additional shift register enables fast serial writing and reading of data in the memory. Such a memory circuit has the drawback that a large chip surface area is required for the additional on-chip shift register.